VERIFICATION ENGINEER

THE POSITION

As a Verification Engineer, your daily work will consist of verifying ASIC/FPGA projects in HDL code (VHDL, Verilog, SystemVerilog) based on functional requirements, i.e. independent from the implementation.

The ability to define the verification environment architecture in SystemVerilog language, according to UVM methodology, is required. Applicants should be able to design UVM verification components (UVC) and to integrate components in a more complex verification environment.

RESPONSIBILITIES:

• Test Plan Development: Create comprehensive verification plans based on design specifications.

• Simulation: Develop and run simulations using tools like SystemVerilog, UVM, or VHDL.

• Testbench Design: Build and maintain testbenches for functional and system-level verification.

• Debugging: Identify and resolve issues in the design through systematic debugging.

• Coverage Analysis: Ensure thorough testing by analyzing functional and code coverage metrics.

• Automation: Develop scripts and frameworks to automate verification processes.

• Collaborative Testing: Work with design, FPGA, and software teams to verify functionality and resolve discrepancies.

• Regression Testing: Set up and run regression tests to ensure design stability across updates.

• Documentation: Generate verification reports and document test methodologies.

• Tool Proficiency: Use industry-standard verification tools like Cadence, Synopsys, or Mentor Graphics.

TECHNICAL REQUIREMENTS:

• Computer architectures and digital systems

• FPGA architectures and related implementation flow

• HDL languages: SystemVerilog, Verilog and VHDL

• UVM methodology

• FPGA development tools: Quartus, Vivado, Libero SoC

• Simulators: MG Questa Prime, Synopsys VCS and Verdi, Cadence Xcelium

• Constraining and timing analysis skills

• Programming languages: C / C ++ (advanced skills)

• Scripting languages: python, bash

• Oral English skills are mandatory

Preferred knowledge and skills:

• Experience in complex Verification Environment development

• Experience in the development of functional models and covergroup/point and bins definition

• Signal processing algorithms

ABOUT YOU:

• Strategic, pragmatic, analytical, and technical thinking.

• Exceptional judgment, tact, and decision-making ability.

• Highly organized, ability to prioritize tasks and detail-oriented.

• Innovative mindset and proactivity,

• Flexibility to adjust to multiple demands, shifting priorities, ambiguity, and rapid change.

• Excellent ability to work as a team player and have a collaborative attitude